Description

   The AT9554 and AT9554A are 16-pin CMOS devices that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I²C-bus/SMBus applications.The improvements include higher drive capability, 5V I/O tolerance, lower supply current,individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, and so on.

    The AT9554/AT9554A consist of an 8-bit Configuration register (Input or Output selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. Although pin-to-pin and I²C-bus address compatible with the AT8574 series, software changes are required due to the enhancements.

    The AT9554/AT9554A open-drain interrupt output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine.

    Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address and allow up to eight devices to share the same I²C-bus/SMBus. The AT9554A is identical to the AT9554 except that the fixed I²C-bus address is different allowing up to sixteen of these devices(eight of each) on the same I²C-bus/SMBus.

Features

• Operating power supply voltage range of 2.3V to 5.5 V

• 5V tolerant I/Os

• Polarity Inversion register

• Active LOW interrupt output

• Low standby current

• Noise filter on SCL/SDA inputs

• No glitch on power-up

• Internal power-on reset

• 8 I/O pins which default to 8 inputs

• 0 Hz to 400 kHz clock frequency

• ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM perJESD22-C101

• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

• AEC-Q100 compliance available

• Packages offered: SO16, SSOP16, SSOP20, TSSOP16, HVQFN16 (2 versions:4x4x 0.85 mm and 3x 3 x 0.85 mm), and bare die

Typical Application